Datasheet4U Logo Datasheet4U.com

74LS155 - Dual 2-Line to 4-Line Decoders/Demultiplexers

Description

These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package.

Features

  • s.

📥 Download Datasheet

Datasheet preview – 74LS155

📁 Similar Datasheet

  • 74LS155 - DUAL 1-OF-4 DECODER/ DEMULTIPLEXER (ON Semiconductor)
  • 74LS155 - Dual 2-line-to-4-line Decoders/Demultiplexers (Hitachi Semiconductor)
  • 74LS155 - DUAL 1-OF-4 DECODER/DEMULTIPLEXER (Motorola)
  • 74LS155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (National Semiconductor)
  • 74LS155A - Dual 2-Line To 4-Line Decoders/Demultiplexers (Texas Instruments)
  • 74LS15 - TRIPLE 3-INPUT AND GATE (Motorola)
  • 74LS151 - LOW POWER SCHOTTKY (ON Semiconductor)
  • 74LS151 - 1-of-8 Data Selectors/Multiplexers (Hitachi Semiconductor)
  • 74LS151 - 8-INPUT MULTIPLEXER (Motorola)
  • 74LS152 - HD74LS152 (Renesas Technology)
Other Datasheets by Fairchild Semiconductor
  • 74LS150 - Data Selectors/Multiplexers
  • 74LS151 - 1-of-8 Line Data Selector/Multiplexer
  • 74LS153 - Dual 1-of-4 Line Data Selectors/Multiplexers
  • 74LS154 - 4-Line to 16-Line Decoder/Demultiplexer
  • 74LS156 - Dual 2-Line to 4-Line Decoders/Demultiplexers
  • 74LS10 - Triple 3-Input NAND Gate
  • 74LS11 - Triple 3-Input AND Gate
  • 74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

Full PDF Text Transcription

Click to expand full text
DM74LS155 • DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers August 1986 Revised April 2000 DM74LS155 • DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers General Description These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs.
Published: |